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<a name="details" id="details"></a><h2 class="groupheader">Overview</h2>
<div class="textblock"><p>This is the header file which contains versalnet specific definitions for the PDI. </p>
<pre>
MODIFICATION HISTORY:</pre><pre>Ver   Who  Date        Changes
----- ---- -------- -------------------------------------------------------
1.00  bm   07/06/2022 Initial release
      bm   07/13/2022 Added compatibility check for In-Place PLM Update
      bm   09/13/2022 Added macros for maximum number of partitions and images
1.01  har  11/17/2022 Added macros for Signed Image attribute in Bootheader
      ng   11/23/2022 Fixed doxygen file name error
      sk   01/11/2023 Added macro for Image Store as SBD
1.02  ng   04/27/2023 Added support for cluster flags in ATF handoff params
      sk   07/09/2023 Added defines for TCM Boot Enable Bit, Mask
      am   07/10/2023 Moved IHT OP data macros to common <a class="el" href="xilpdi_8h.html" title="This is the header file which contains definitions for the PDI. ">xilpdi.h</a> file
      kpt  12/04/2023 Added <a class="el" href="struct_xil_pdi___boot_hdr.html" title="Structure to store the boot header table details. ">XilPdi_BootHdr</a>
2.01  mb   08/10/2024 Added macro for JTAG as SBD.</pre><pre></pre><dl class="section note"><dt>Note</dt><dd></dd></dl>
</div><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_pdi___boot_hdr_fw_rsvd.html">XilPdi_BootHdrFwRsvd</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure to store the Boot Header PMC FW fields.  <a href="struct_xil_pdi___boot_hdr_fw_rsvd.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_pdi___boot_hdr.html">XilPdi_BootHdr</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure to store the boot header table details.  <a href="struct_xil_pdi___boot_hdr.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_pdi___img_hdr_tbl.html">XilPdi_ImgHdrTbl</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure to store the image header table details.  <a href="struct_xil_pdi___img_hdr_tbl.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="struct_xil_pdi___prtn_hdr.html">XilPdi_PrtnHdr</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure to store the partition header details.  <a href="struct_xil_pdi___prtn_hdr.html#details">More...</a><br/></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
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<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="member-group"></a>
XilPdi Definitions</h2></td></tr>
<tr class="memitem:a20549f45008255d3f437889e03adb476"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#a20549f45008255d3f437889e03adb476">XIH_BH_IMG_ATTRB_SIGNED_IMG_MASK</a>&#160;&#160;&#160;(0xC0000U)</td></tr>
<tr class="memdesc:a20549f45008255d3f437889e03adb476"><td class="mdescLeft">&#160;</td><td class="mdescRight">Boot header Attr fields.  <a href="#a20549f45008255d3f437889e03adb476">More...</a><br/></td></tr>
<tr class="separator:a20549f45008255d3f437889e03adb476"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_BH_IMG_ATTRB_SIGNED_IMG_SHIFT</b>&#160;&#160;&#160;(18U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_BH_IMG_ATTRB_SIGNED_IMG_VALUE</b>&#160;&#160;&#160;(0x3U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_MAX_PRTNS</b>&#160;&#160;&#160;(32U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_MAX_IMGS</b>&#160;&#160;&#160;(32U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_MASK</b>&#160;&#160;&#160;(0xFC0U)</td></tr>
<tr class="separator:ab8370747cfc069f91966249547566495"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SHIFT</b>&#160;&#160;&#160;(0x6U)</td></tr>
<tr class="separator:a258ac860eec21997dadad867187e5439"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SAME</b>&#160;&#160;&#160;(0x0U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_QSPI32</b>&#160;&#160;&#160;(0x1U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_QSPI24</b>&#160;&#160;&#160;(0x2U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SDLS_B0</b>&#160;&#160;&#160;(0x4U)</td></tr>
<tr class="separator:a9b445c3b07d787d0c38068ea1a6676b6"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SD_B1</b>&#160;&#160;&#160;(0x5U)</td></tr>
<tr class="separator:aa742676fd181e97a489b50818a1ebf3d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a883baac990f957560b22293617c99e2f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a883baac990f957560b22293617c99e2f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SDLS_B1</b>&#160;&#160;&#160;(0x6U)</td></tr>
<tr class="separator:a883baac990f957560b22293617c99e2f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a18b02385c027ea4f03055dd4a28a3b93"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a18b02385c027ea4f03055dd4a28a3b93"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_EMMC</b>&#160;&#160;&#160;(0x7U)</td></tr>
<tr class="separator:a18b02385c027ea4f03055dd4a28a3b93"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_USB</b>&#160;&#160;&#160;(0x8U)</td></tr>
<tr class="separator:a4dce094203cfba0c1b336ff72b471d18"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_PCIE</b>&#160;&#160;&#160;(0xAU)</td></tr>
<tr class="separator:afdd6a894caf34bd8101806b49ab33df2"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad6e975c0112ff0949350b3a0ca1efa5b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad6e975c0112ff0949350b3a0ca1efa5b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_OSPI</b>&#160;&#160;&#160;(0xCU)</td></tr>
<tr class="separator:ad6e975c0112ff0949350b3a0ca1efa5b"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SMAP</b>&#160;&#160;&#160;(0xDU)</td></tr>
<tr class="separator:ae540bd03f91284179ab22d6caabdbe40"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ab84bbe41503a52b8cb297d99c0bb86ee"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ab84bbe41503a52b8cb297d99c0bb86ee"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_JTAG</b>&#160;&#160;&#160;(0xEU)</td></tr>
<tr class="separator:ab84bbe41503a52b8cb297d99c0bb86ee"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a72ac8e20fb2617ea7d7d4e89021ff248"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a72ac8e20fb2617ea7d7d4e89021ff248"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SDLS_B0_RAW</b>&#160;&#160;&#160;(0xFU)</td></tr>
<tr class="separator:a72ac8e20fb2617ea7d7d4e89021ff248"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a5337da4b7e09a697d250323a6a34683f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5337da4b7e09a697d250323a6a34683f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SD_B1_RAW</b>&#160;&#160;&#160;(0x10U)</td></tr>
<tr class="separator:a5337da4b7e09a697d250323a6a34683f"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_SDLS_B1_RAW</b>&#160;&#160;&#160;(0x11U)</td></tr>
<tr class="separator:a1ccccdfb66078b5aa1af97bad3faaee5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4832d2dfefa66d1d43a87cc26a468ce5"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4832d2dfefa66d1d43a87cc26a468ce5"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_EMMC_RAW</b>&#160;&#160;&#160;(0x12U)</td></tr>
<tr class="separator:a4832d2dfefa66d1d43a87cc26a468ce5"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7931b33bcedbbe5ceb58d2be580751bb"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7931b33bcedbbe5ceb58d2be580751bb"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_EMMC_0</b>&#160;&#160;&#160;(0x13U)</td></tr>
<tr class="separator:a7931b33bcedbbe5ceb58d2be580751bb"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a74d210777836a0511abd04ba28ce7683"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a74d210777836a0511abd04ba28ce7683"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_SBD_EMMC_0_RAW</b>&#160;&#160;&#160;(0x14U)</td></tr>
<tr class="separator:a74d210777836a0511abd04ba28ce7683"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad892adfe9c2f06beebd802c6679b5764"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad892adfe9c2f06beebd802c6679b5764"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_IHT_ATTR_IMAGE_STORE</b>&#160;&#160;&#160;(0x15U)</td></tr>
<tr class="separator:ad892adfe9c2f06beebd802c6679b5764"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a1c23aa3bfeb4a296c35a73b9c1b79b08"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#a1c23aa3bfeb4a296c35a73b9c1b79b08">XIH_PH_ATTRB_HIVEC_MASK</a>&#160;&#160;&#160;(0x800000U)</td></tr>
<tr class="memdesc:a1c23aa3bfeb4a296c35a73b9c1b79b08"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prtn Attribute fields.  <a href="#a1c23aa3bfeb4a296c35a73b9c1b79b08">More...</a><br/></td></tr>
<tr class="separator:a1c23aa3bfeb4a296c35a73b9c1b79b08"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a068bc32606e7a770cb187d2b047fa788"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a068bc32606e7a770cb187d2b047fa788"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_ENDIAN_MASK</b>&#160;&#160;&#160;(0x40000U)</td></tr>
<tr class="separator:a068bc32606e7a770cb187d2b047fa788"><td class="memSeparator" colspan="2">&#160;</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CLUSTER_MASK</b>&#160;&#160;&#160;(0x00C0U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_CLUSTER_LOCKSTEP_MASK</b>&#160;&#160;&#160;(0x0030U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_A78_EXEC_ST_MASK</b>&#160;&#160;&#160;(0x0008U)</td></tr>
<tr class="separator:a69dd2d370f8d380fb2da32890d41d755"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3e3bb09567627f3a0f0b8d329040beda"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3e3bb09567627f3a0f0b8d329040beda"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CLUSTER_SHIFT</b>&#160;&#160;&#160;(6U)</td></tr>
<tr class="separator:a3e3bb09567627f3a0f0b8d329040beda"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abb4e56461afc7bf358d01682cb4105ad"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="abb4e56461afc7bf358d01682cb4105ad"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_TCM_BOOT_MASK</b>&#160;&#160;&#160;(0x180000U)</td></tr>
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<tr class="memitem:ad2b34f8a94535a70a9cf14898261181f"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#ad2b34f8a94535a70a9cf14898261181f">XIH_PH_ATTRB_PRTN_TYPE_RSVD</a>&#160;&#160;&#160;(0x0000000U)</td></tr>
<tr class="memdesc:ad2b34f8a94535a70a9cf14898261181f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Prtn Attribute Values.  <a href="#ad2b34f8a94535a70a9cf14898261181f">More...</a><br/></td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_PRTN_TYPE_ELF</b>&#160;&#160;&#160;(0x1000000U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_PRTN_TYPE_CDO</b>&#160;&#160;&#160;(0x2000000U)</td></tr>
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<tr class="memitem:aabacf40da5795b93b64f865838a583a2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aabacf40da5795b93b64f865838a583a2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_PRTN_TYPE_CFI_GSC_UNMASK</b>&#160;&#160;&#160;(0x7000000U)</td></tr>
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<tr class="memitem:a32873589c2f891a5ed3a90e6430e0c70"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a32873589c2f891a5ed3a90e6430e0c70"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_PRTN_OWNER_PLM</b>&#160;&#160;&#160;(0x00000U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_HASH_SHA3</b>&#160;&#160;&#160;(0x3000U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_NONE</b>&#160;&#160;&#160;(0x0000U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CLUSTER_0</b>&#160;&#160;&#160;(0x000U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CLUSTER_1</b>&#160;&#160;&#160;(0x040U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CLUSTER_2</b>&#160;&#160;&#160;(0x080U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CLUSTER_3</b>&#160;&#160;&#160;(0x0C0U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_DSTN_CLUSTER_0</b>&#160;&#160;&#160;(0x000U)</td></tr>
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#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_DSTN_CLUSTER_1</b>&#160;&#160;&#160;(0x001U)</td></tr>
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<tr class="memitem:a5677b8094420172499858f0c0b998d08"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a5677b8094420172499858f0c0b998d08"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_DSTN_CLUSTER_2</b>&#160;&#160;&#160;(0x002U)</td></tr>
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<tr class="memitem:ad4ff03848810421bd47298152253fd6f"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ad4ff03848810421bd47298152253fd6f"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_DSTN_CLUSTER_3</b>&#160;&#160;&#160;(0x003U)</td></tr>
<tr class="separator:ad4ff03848810421bd47298152253fd6f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a452b51382ea4145f8e798f58d607180b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a452b51382ea4145f8e798f58d607180b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_CLUSTER_LOCKSTEP_ENABLED</b>&#160;&#160;&#160;(0x030U)</td></tr>
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<tr class="memitem:a687fb8533305e16370711a45f9446b48"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a687fb8533305e16370711a45f9446b48"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_CLUSTER_LOCKSTEP_DISABLED</b>&#160;&#160;&#160;(0x000U)</td></tr>
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<tr class="memitem:a8c44a84fbef12552230cb5d5b046dedc"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8c44a84fbef12552230cb5d5b046dedc"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_A78_0</b>&#160;&#160;&#160;(0x100U)</td></tr>
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<tr class="memitem:a546f1c518f2cfdce4f3ecdea73a13c6e"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a546f1c518f2cfdce4f3ecdea73a13c6e"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_A78_1</b>&#160;&#160;&#160;(0x200U)</td></tr>
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<tr class="memitem:a3a5821e50916a0e03526630f7b34d237"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3a5821e50916a0e03526630f7b34d237"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_A78_2</b>&#160;&#160;&#160;(0x300U)</td></tr>
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<tr class="memitem:a50d979df0fd0162fa3276cb3e0611dc7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a50d979df0fd0162fa3276cb3e0611dc7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_A78_3</b>&#160;&#160;&#160;(0x400U)</td></tr>
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<tr class="memitem:a1cae5715ca987bb018e00220b6d77b92"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1cae5715ca987bb018e00220b6d77b92"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_R52_0</b>&#160;&#160;&#160;(0x500U)</td></tr>
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<tr class="memitem:ac8be8a1c333700ee2eb5864fad9cc5bd"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="ac8be8a1c333700ee2eb5864fad9cc5bd"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_R52_1</b>&#160;&#160;&#160;(0x600U)</td></tr>
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<tr class="memitem:a1cf5256e3ae0a3e3160b87a6633be4fa"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a1cf5256e3ae0a3e3160b87a6633be4fa"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_DSTN_CPU_PSM</b>&#160;&#160;&#160;(0x800U)</td></tr>
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<tr class="memitem:aee26331073f509c2b65a9eb26d91b1cf"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee26331073f509c2b65a9eb26d91b1cf"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PH_ATTRB_TCM_BOOT_ENABLED</b>&#160;&#160;&#160;(0x180000U)</td></tr>
<tr class="separator:aee26331073f509c2b65a9eb26d91b1cf"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a40b2c1e61725ae3bc034f8d15f3edf60"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#a40b2c1e61725ae3bc034f8d15f3edf60">XIH_ATTRB_A78_EXEC_ST_SHIFT_DIFF</a>&#160;&#160;&#160;(3U)</td></tr>
<tr class="memdesc:a40b2c1e61725ae3bc034f8d15f3edf60"><td class="mdescLeft">&#160;</td><td class="mdescRight">Below is the bit mapping of fields in the ATF Handoff parameters with that of Prtn header.  <a href="#a40b2c1e61725ae3bc034f8d15f3edf60">More...</a><br/></td></tr>
<tr class="separator:a40b2c1e61725ae3bc034f8d15f3edf60"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a3a6d398e62c5c09f937fc889df4b9188"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a3a6d398e62c5c09f937fc889df4b9188"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_ENDIAN_SHIFT_DIFF</b>&#160;&#160;&#160;(17U)</td></tr>
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<tr class="memitem:a15d176990fac32cf8374da7f01984b2c"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a15d176990fac32cf8374da7f01984b2c"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_TR_SECURE_SHIFT_DIFF</b>&#160;&#160;&#160;(2U)</td></tr>
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<tr class="memitem:aaac5d8c16ae9c8ca0cbac041125bed8b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aaac5d8c16ae9c8ca0cbac041125bed8b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_TARGET_EL_SHIFT_DIFF</b>&#160;&#160;&#160;(2U)</td></tr>
<tr class="separator:aaac5d8c16ae9c8ca0cbac041125bed8b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afe3513e829a8dec911924607a98f1b61"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afe3513e829a8dec911924607a98f1b61"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_DSTN_CLUSTER_SHIFT_DIFF</b>&#160;&#160;&#160;(0x5U)</td></tr>
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<tr class="memitem:afb13cbd7e5e007d2eb39a180ff8534d7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="afb13cbd7e5e007d2eb39a180ff8534d7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_ATTRB_EL_MASK</b>&#160;&#160;&#160;(0x18U)</td></tr>
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<tr class="memitem:a97e5ba36bf33dd1415b46b674a3f1cf7"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a97e5ba36bf33dd1415b46b674a3f1cf7"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_EL_2</b>&#160;&#160;&#160;(0x10U)</td></tr>
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<tr class="memitem:a15bdcfb0d1638257518b7950d49e3bd1"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a15bdcfb0d1638257518b7950d49e3bd1"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_EL_3</b>&#160;&#160;&#160;(0x18U)</td></tr>
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<tr class="memitem:acdbf54149226104f4519948dfd5ec7c8"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="acdbf54149226104f4519948dfd5ec7c8"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_DSTN_CPU_A78_0</b>&#160;&#160;&#160;(0x00U)</td></tr>
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<tr class="memitem:a4af7525e929fda4fa71c5370e90234b2"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a4af7525e929fda4fa71c5370e90234b2"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_DSTN_CPU_A78_1</b>&#160;&#160;&#160;(0x20U)</td></tr>
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<tr class="memitem:aace9094d8279ff77be02b0c93f52ea54"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aace9094d8279ff77be02b0c93f52ea54"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_DSTN_CPU_A78_2</b>&#160;&#160;&#160;(0x40U)</td></tr>
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<tr class="memitem:a8a3a0f8a98f6043308222a8d4a7a6b4b"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a8a3a0f8a98f6043308222a8d4a7a6b4b"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_PRTN_FLAGS_DSTN_CPU_A78_3</b>&#160;&#160;&#160;(0x60U)</td></tr>
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<tr class="memitem:a351bff832c12cc8b15dc7dfc48466dfe"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a351bff832c12cc8b15dc7dfc48466dfe"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_OPTIONAL_DATA_LEN_OFFSET</b>&#160;&#160;&#160;(0x58U)</td></tr>
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<tr class="memitem:a7aff05bfefb04b4412302f9f1c40e571"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="a7aff05bfefb04b4412302f9f1c40e571"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_OPT_DATA_NON_DATA_LEN</b>&#160;&#160;&#160;(8U)</td></tr>
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<tr class="memitem:aee6cc0a34ff814c9516e3d510f1e0b94"><td class="memItemLeft" align="right" valign="top"><a class="anchor" id="aee6cc0a34ff814c9516e3d510f1e0b94"></a>
#define&#160;</td><td class="memItemRight" valign="bottom"><b>XIH_OPT_DATA_STRUCT_INFO_ID</b>&#160;&#160;&#160;(2U)</td></tr>
<tr class="separator:aee6cc0a34ff814c9516e3d510f1e0b94"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:abe0eb8b87843a088c0ec15d589f47ade"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#abe0eb8b87843a088c0ec15d589f47ade">XIH_BH_META_HDR_OFFSET</a>&#160;&#160;&#160;(0xC4U)</td></tr>
<tr class="memdesc:abe0eb8b87843a088c0ec15d589f47ade"><td class="mdescLeft">&#160;</td><td class="mdescRight">Offset to the metaheader offset field present in boot header.  <a href="#abe0eb8b87843a088c0ec15d589f47ade">More...</a><br/></td></tr>
<tr class="separator:abe0eb8b87843a088c0ec15d589f47ade"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad49a1171235ff234ce6053c13c341363"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#ad49a1171235ff234ce6053c13c341363">XIH_BH_PRAM_ADDR</a>&#160;&#160;&#160;(0xF201E000U)</td></tr>
<tr class="memdesc:ad49a1171235ff234ce6053c13c341363"><td class="mdescLeft">&#160;</td><td class="mdescRight">Boot header address in PRAM copied by ROM.  <a href="#ad49a1171235ff234ce6053c13c341363">More...</a><br/></td></tr>
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<tr class="memitem:afed5d9eda2658b7622bd5f2c8da260aa"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#afed5d9eda2658b7622bd5f2c8da260aa">XIH_BH_PUF_HD_OFFSET</a>&#160;&#160;&#160;(0x918U)</td></tr>
<tr class="memdesc:afed5d9eda2658b7622bd5f2c8da260aa"><td class="mdescLeft">&#160;</td><td class="mdescRight">Boot header PUF fields.  <a href="#afed5d9eda2658b7622bd5f2c8da260aa">More...</a><br/></td></tr>
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<tr class="memitem:a254f57817c8e9540de61c680ea8cc5ca"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#a254f57817c8e9540de61c680ea8cc5ca">XIH_BH_PUF_CHASH_OFFSET</a>&#160;&#160;&#160;(0xF18U)</td></tr>
<tr class="memdesc:a254f57817c8e9540de61c680ea8cc5ca"><td class="mdescLeft">&#160;</td><td class="mdescRight">BootHeader PUF CHASH offset.  <a href="#a254f57817c8e9540de61c680ea8cc5ca">More...</a><br/></td></tr>
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<tr class="memitem:ab22fd434f45031b985604716b4eafa4e"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="net_2xilpdi__plat_8h.html#ab22fd434f45031b985604716b4eafa4e">XIH_BH_PUF_AUX_OFFSET</a>&#160;&#160;&#160;(0xF1CU)</td></tr>
<tr class="memdesc:ab22fd434f45031b985604716b4eafa4e"><td class="mdescLeft">&#160;</td><td class="mdescRight">BootHeader PUF auxiliary offset.  <a href="#ab22fd434f45031b985604716b4eafa4e">More...</a><br/></td></tr>
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<h2 class="groupheader">Macro Definition Documentation</h2>
<a class="anchor" id="a40b2c1e61725ae3bc034f8d15f3edf60"></a>
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          <td class="memname">#define XIH_ATTRB_A78_EXEC_ST_SHIFT_DIFF&#160;&#160;&#160;(3U)</td>
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<p>Below is the bit mapping of fields in the ATF Handoff parameters with that of Prtn header. </p>
<p>The number of bits shifted is is based on the difference between these two offsets </p>
<pre class="fragment">              ATFHandoffParams     PrtnHdr              Shift
</pre> <h2>Parameter PrtnFlags PrtnAttrb difference </h2>
<p>Exec State 0 3 3 right ENDIAN 1 18 17 right SECURE 2 0 2 left EL 3:4 1:2 2 left CPU_A78 5:6 8:11 Cluster# 11:12 6:7 5 left </p>

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          <td class="memname">#define XIH_BH_IMG_ATTRB_SIGNED_IMG_MASK&#160;&#160;&#160;(0xC0000U)</td>
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<p>Boot header Attr fields. </p>

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          <td class="memname">#define XIH_BH_META_HDR_OFFSET&#160;&#160;&#160;(0xC4U)</td>
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<p>Offset to the metaheader offset field present in boot header. </p>

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          <td class="memname">#define XIH_BH_PRAM_ADDR&#160;&#160;&#160;(0xF201E000U)</td>
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<p>Boot header address in PRAM copied by ROM. </p>

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          <td class="memname">#define XIH_BH_PUF_AUX_OFFSET&#160;&#160;&#160;(0xF1CU)</td>
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<p>BootHeader PUF auxiliary offset. </p>

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          <td class="memname">#define XIH_BH_PUF_CHASH_OFFSET&#160;&#160;&#160;(0xF18U)</td>
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<p>BootHeader PUF CHASH offset. </p>

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          <td class="memname">#define XIH_BH_PUF_HD_OFFSET&#160;&#160;&#160;(0x918U)</td>
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<p>Boot header PUF fields. </p>
<p>BootHeader PUF HD offset. </p>

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          <td class="memname">#define XIH_PH_ATTRB_HIVEC_MASK&#160;&#160;&#160;(0x800000U)</td>
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<p>Prtn Attribute fields. </p>

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          <td class="memname">#define XIH_PH_ATTRB_PRTN_TYPE_RSVD&#160;&#160;&#160;(0x0000000U)</td>
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<p>Prtn Attribute Values. </p>

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